Difference between revisions of "Formal verification"
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Revision as of 12:08, 26 August 2016
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics.
Description
Formal verification can be helpful in proving the correctness of systems such as:
- Cryptographic protocols
- Combinational circuits
- Digital circuits with internal memory
- Software expressed as source code.
The verification of these systems is done by providing a formal proof on an abstract mathematical model of the system, the correspondence between the mathematical model and the nature of the system being otherwise known by construction.
Examples of mathematical objects often used to model systems include:
- Finite-state machines
- Labelled transition systems
- Petri nets
- Vector addition systems
- Timed automata
- Hybrid automata
- Process algebra
- Formal semantics of programming languages such as operational semantics
- Denotational semantics
- Axiomatic semantics
- Hoare logic
See also
- Automated theorem proving
- Formal equivalence checking
- Intelligent verification
- List of model checking tools
- LURCH
- Model checking
- Post silicon validation
- Program synthesis
- Proof checker
- Property Specification Language
- Runtime verification
- Selected formal verification bibliography
- Static code analysis
- Temporal logic in finite-state verification
External links
- Formal verification @ Wikipedia
